Very Deep Submicron GHz CAM Full Custom Design

The tag of the TLB(Translation Look-Aside Buffer) on the critical path of Microprocessor Core contains Data Array and Tag Array. Data array is generally implemented by SRAM(Static Random Access Memory), and Tag array is generally implemented by CAM (Content-Addressable Memory). The CAM enables TLB to speed up the virtual reality address translation through parallel and express comparison, which greatly impact on the microprocessor performance. To design CAM by full-custom design is being with the characteristics of faster speed and smaller size, which has wide range of application value and important significance.The writer of this paper deeply studied the full-custom CAM technology, and designed CAM that meets the performance requirements of TLB. The writer designed this high-performance CAM in 0.13μm CMOS by optimizing CAM circuit parameters, physical map and many other aspects.The Main contribution and innovative points of this paper are given in the following.1,Full-custom implementation of the CAM in the TLB. The match operation and address decoding are operated in the pos-edge of CLK, The read operation, write operation, and pre-charge of local match-lines and global match-lines are operated in the negative edge of CLK. At the worst cases, layout simulation show that the operating frequency of 1GHz, read operation 640.12ps, write operation 574.35ps, match operation 360ps, area 0.21mm2.2,Optimized and improved a new match-line structure, inverter control hierarchical match-line structure. This structure can faster pull down local match line than normal structure, thereby being with better matching performance.3,Optimized structural design of dual match-line. Differential voltage sensitive amplifier will be applied to the dual match-line structure, faster than before to optimize the speed of the CAM operation.