The Research On Function-level Hardware/software Co-design Programming Model Based On Reconfigurable System On Chip

Benefit from the rapid development of IC manufacturing technology, field programmable gate array technology has made remarkable progress and continues to develop further. Microprocessor, variable logic devices and other important components can form a complex and highly integrated reconfigurable system on chip (RSOC).RSOC design technology is legging behind that of the device's development. Function-level hardware/software co-design method is applied to lift lagging design capability. Function-level co-design method requires programming model,hardware platform and communication structure support.There are many issues that must be resolved.This article focuses on the field of function-level transparent programming model.In order to achieve transparent programming and raise design efficiency, mainly to complete the following work:First, this paper presents the basic flow and structure of function-level hardware-software co-design method from programming model point of view. Meanwhile,give respective task of target application description,synthesis and operating environment in detail.Target application designers can follow the process to write the target application according to application requirements,and generate an executable binary program that can run on the target application platform.Second, in this paper, we have designed the internal structure of software/hardware co-function and the corresponding implementations of each module.Co-function is the core of function-level hardware/software co-design method.We present co-function's interface and specification in detail,such as the external uniform interface convention of co-function and software interface of hardware modules.We also give the design and implementation way of the key modules of the co-function in a specific example.Then,co-function has special structure;it requires some kind supporting work mechanism,including the generation and registration of constraint information.We design a co-function scheduler to generate co-function runtime constraint information. We provide an analysis of the working model and specific implementations of the co-function scheduler and test the performance of the model's key part. The environment for running executable program is modified.The new environments support the registration of co-function constraint information. Finally, we test the function-level hardware/software co-design method using a example.The resources of currant RSOC are limited.We construct a simple prototype system and verified the feasibility of function-level co-design method from programming model point of view.