A Study On Hardware/Software Co-design Methodology For Reconfigurable System-on-Chip

Reconfigurable System-on-Chip (RSoC) contains components of various functions and architectures with hardware and software together, resulting in the architecture of heterogeneous multiple processing elements, which calls for the EDA tools to support the hardware/software co-design with consideration of such architecture. This thesis focuses on the studies of a new design methodology of RSoC and the related topics of system functional specification, architecture model, partitioning algorithms, as well as system simulation and verification. The main contributions are outlined as follows:1. An automated RSoC design flow based on the hardware/software programming model is proposed. In the programming model, system designers use high-level language to code the functional specification by calling the co-function-library. Then the dynamic hardware/software partitioning algorithm will decide whether an invoked function should be running on hardware or software. According to the partitioning result, the dynamic linker will switch these functions’execution mode in real time. And the above items can facilitate an automated design flow through specification to the system implementation. Experiments and tests proof the feasibility and efficiency of the automated design flow.2. A new hardware/software partitioning methodology combining search space smoothing and discrete particle swarm optimization is proposed. Smoothing effect is obtained through altering the parameters of each component in the system to the average values and guides discrete particle swarm optimization in finding the best solution. Experimental results show prominent improvement in partitioning quality is observed from the test results between the search space smoothing enhanced algorithm and the original one, while the time complexities of the two algorithms are of the same order. This verifies that applying search space smoothing technique is a proper approach to solve the constrained optimization problem in hardware/software partitioning.3. An implementation method of Dynamic Partial Reconfiguration (DPR) on RSoC is proposed. In order to design a DPR system quickly and effectively, the design method of the DPR system based on Early-Access Partial Reconfiguration (EARP) and the PlanAhead tool is focused, and the design flow is also described in detail. Experimental results show that the proposed method could complete the system design of DPR more effectively, and finally the effectiveness and convenience of design method are verified by two specific examples:a DES encryption/decryption and an audio filter system.4. A novel method to accelerate data stream processing using Field Programmable Gate Arrays (FPGA) is proposed. The method uses both hardware and software components (operators), and efficiently partitions a query between these components to achieve a maximum performance gain. The prototype developed is called Symbiote to represent the synergy between hardware and software functionality. The experimental results show that Symbiote can obtain superior performance in highway toll applications, the average processing time for a single tuple is only1/4of that achieved in pure software execution. Since the hardware processor is capable of handling more than one tuple in parallel, so the system in response to the high data rate of complex data stream applications must have more advantages. Good performance of Symbiote can also validate the feasibility and efficiency of the proposed RSoC co-design method, hardware/software partitioning algorithm, and dynamic partial reconfiguration method.