The Research On Function-level Hardware/Software Partitioning Algorithm Based On Reconfigurable System On Chip

The reconfigurable System on Chip's (RSoC) appearance brought a big jump in embedded systems. Reconfigurable system's flexibility, high performance and high reliability make it widely used. It not only provides high-performance hardware, but also has programmable. RSoC can meet user's needs, especially in, the requirement is dynamic change. So that this system is widely used in the aerospace field, encryption system, research and education in embedded system.However, design becomes complex because of the flexibility of reconfigurable system on chip. Especially in while the dynamic reconfiguration technology emerges, which make the reconfigurable system on chip's design capability is inadequate. The most critical step in hardware-software co-design is the HW/SW partitioning. It is a important issue that find a effective partitioning method. This paper focuses on HW/SW partitioning algorithm of hardware-software co-design on RSoC. In this paper the function specifications, granularity level, and hardware-software partitioning algorithm are researched, this thesis does the following work:First of all, a new static HW/SW partitioning algorithm is represented:Based on the process level (function) of the hybrid optimal algorithm, which is constructed by merging particle swarm algorithm with simulated annealing algorithm. The particle swarm algorithm is simple, fast speed, but sometimes fall into local optimum. During very iteration, each particle is update by following two "best" values. The first one is called local best. Aonther is called global best. The mechanism of sharing the information is unidirectional. The information is purposeful which not only can speed up the convergence rate, but also increases the probability of falling into the local optimum. Combined with other search algorithm can improve the search efficiency. Because the simulated annealing algorithm can be out of the local optimum, in this paper a hybrid optimal algorithm is constructed based on the process level (function). Results of experiments show that this optimal algorithm is effective, feasible and stable in the HW/SW portioning.Secondly, a dynamic HW/SW partitioning algorithm is represented:a dynamic HW/SW partitioning algorithm consider the depth of the task node. This algorithm is fully considered in each node in the DAG graph the impact on the subsequent nodes. To consider nodes'execution time and communication time, based on the dependence between the nodes, the depth first search is executed. And that factors into the objective function, so as to achieve the purpose of effectively improving system performance.Finally, two simple prototype systems are designed. According to existing tools and reconfigurable on-chip system resources, the partitioning algorithm is run in a prototype system:including two prototype systems of static and dynamic. The feasibility and effectiveness are verified on the perspective of the entire design process.