Research On Hardware/Software Partitioning Of Security Encryption Chip Based On Reconfigurable System-on-Chip

Security encryption chips are important parts of information systems.They play important roles in protecting the security of military,financial,business and personal information.Since FPGAs have advantages in flexible design and short development cycle,reconfigurable security chips based on RSoC(Reconfiguralbe System-on-Chip)have been paid more and more attention to.Effective hardware/software(HW/SW)partitioning can make better use of CPU core and reconfigurable logic the two computing resources in security RSoC and achieve better performance.Therefore,research on HW/SW partitioning of reconfigurable security encryption chip based on RSoC has important significance.Security encryption chips often affect the implementation of the system function modules during self-protection.This paper takes into account the problem that two resisting power analysis attack technologies which are software masking and WDDL(Wave Dynamic Differential Logic)technology affect the implementation of function modules in security RSoC,and studies the dual and multi-way HW/SW partitioning of security RSoC in single CPU and dual-CPU two cases to abtain much better performance under constraint hardware resource.Detailed works are as follows:For security RSoC contains single CPU,the paper designs a dual-way HW/SW partitioning method based on improved simulated annealing algorithm(SA).According to different implementations of tasks,HW/SW partitioning models of Pmh(tasks implemented in masking or hardware mode)and Pdh(tasks implemented on WDDL CPU or hardware)two partitioning ways are established respectively.Then the integration algorithm of greedy and SA is used to solve the HW/SW partitioning problem.In SA,the acceptance criteria is modified to guide the search process,thus to improve the quality of partitioning results.For security RSoC contains dual-CPU,the paper designs a simulated annealing multi-way HW/SW partitioning method based on scheduling evaluation method.There are Pddh,Pdmh and Pmmh three partitioning ways according to different implementations of tasks.In order to better excavate the parallelism among hardware and software tasks,a new evaluation method of a scheduling algorithm based on the priorities of task nodes' depth in DAG graph is given to calculate the goal value of HW/SW partitioning.In the basis of scheduling evaluation method,SA is used to search for the HW/SW partitioning results of the three partitioning ways.For purpose of verifying the effectiveness of partitioning methods and partitioning results,the paper conducts simulation experiments on dual and multi-way HW/SW partitioning respectively and analyzes the experimental results.In dual-way HW/SW partitioning,the improved SA is stable and can search for better partitioning results without increasing the time complexity,moreover,Pdh can get better partitioning results than Pmh.In multi-way HW/SW partitioning,priority scheduling evaluation method can well excavate the parallelism among hardware and software tasks and obtain better system performance,system execution time after partitioning of Pddh is minimum while Pmmh is maximum,Pdmh is in the middle.