Research On Function-Level Design Method For Dynamic Reconfigurable System-on-Chip

Reconfigurable System on Chip (RSoC) takes advantage of both GPP (General Purpose Processors) and ASIC (Application Specific Intergrated Circuits), hence it can provide high performance and programmability, and has become a research hotspot in recent years. Because of these wonderful characteristics including the excellent performance, high reliability and rich flexibleness, the Dynamically Reconfigurable Computing (DRC) system is used extensively in many fields, such as data encryption and decryption, aerospace, computer-aided design, etc.However, there are still many problems in the practical applications of RSoC. First of all, the existing programming models of RSoC are complex. Development process depends on the application programmer's experience which may be a great burden to the software designers and may decrease designers' efficiency; Secondly, designers need to know the architectural and physical details of reconfigurable device. Because there are a lot of different applications, optimization of the hardware module of reconfigurable structure for specific applications will also be a task of designers; Finally, it is still perative to resolve the design automation problem. In view of the characteristics of reconfigurable systems, research and development are needed to develop tools to support automatic task partitioning, algorithm mapping and design optimization.This thesis focuses on the studies of hardware transparent programming model, problem oriented hardware-software co-design and the related topics of system representation, hardware method encapsulation, partitioning algorithms, as well as dynamic linkage between hardware method and soft method. The main contributions are outlined as follows:1. A new method-level(function-level) hardware transparent programming model is proposed, which uses Java for system specification. This model bases on software/hardware method library that allows program designers develop applications by calling software methods regardless of underlying physical details, which will be the infrastructure for dynamic hardware/software partition.2. A way of hardware method encapsulation and the corresponding detailed flow are proposed. Hardware method encapsulation effectively shields how to implement the hardware accelerator's logic function, as well as details of communication and synchronization. In addtion it can help application programmers to optimize their design by designing a domain-oriented hardware-software method library.3. A run-time reconfigurable Java virtual machine has been designed and implemented. The virtual machine loads and links hardware methods according to hardware/software partitioning results, so as to simplify the compiler and synthesis tools, and improve the proficiency of automation.The experimental results show that the above programming model can support the hardware transparent programming, at the same time system performance has been improved. The initial results obtained from this experiment have laid a good foundation for further research, and we've also accumulated some practical experience.