Research On Function Division And Cooperation Of Reconfigurable MPSoC

Reconfigurable Multi-Processor System-on-Chip (MPSoC) consists of general purpose processor cores and reconfigurable logic units which dedicated to application specific hardware task modules or application specific instruction processors. It can not only provide high performance with low power consumption, but also can be reconfigured to adapt to new application scenarios. It will be the mainstream design ideas of the embedded systems in the future.The emergence of new technology brings challenges of program development. In order to give full play to the computing ability of reconfigurable MPSoC, tasks should be divided and scheduled in a reasonable way. Software tasks fit to run on general purpose processor cores and hardware tasks fit to be planned onto reconfigurable logic unit must be distinguished carefully. Dynamic mapping between tasks and computing elements should be determined. Efficient and flexible communication mechanism must be designed to support the interaction among tasks. Hardware/software task partitioning, task scheduling, and inter-task communication are three key issues in the design of reconfigurable MPSoC.The key issues mentioned above are analyzed in depth in this thesis. The main research works and innovational features include:(1) Task partitioning and scheduling problem in design phase of reconfigurable MPSoC is analyzed in depth, and a solution dedicated to the problem is proposed. Hardware/Software co-synthesis is required to generate the operation scheme in the program design phase. In traditional synthesis process, task partitioning process and scheduling process are executed separately. The dependencies between tasks and concurrencies of computing elements are neglected, hence it is hard to guarantee the efficiency of the entire task set. An efficient static hardware/software task partitioning and scheduling algorithm are proposed in this thesis. The algorithm combines the traditional task partitioning process and task scheduling process. The algorithm generates the task partition scheme and task schedule sequence in conjunction, while the cost of the algorithm is only equivalent to traditional task scheduling algorithm.(2) The scheduling problem of dynamic application program sequence in the running phase of reconfigurable MPSoC is analyzed in depth, and a solution dedicated to the problem is proposed. Reconfigurable MPSoC should execute a series of applications in the running phase. Each application is pre-partitioned, and can be accelerated using hardware. Because of the limitation of hardware resources, running scheme of each application should be determined dynamically, and hardware resources should be dispatched to applications reasonably to reduce the execution time of application sequence. An efficient scheduling algorithm for dynamic application sequence is proposed in this thesis. The algorithm determines the running scheme for each application with the historical information. The viability and potential of the proposed algorithm is demonstrated by experimental result.(3) Inter-task communication among hardware and software tasks are analyzed in depth and the corresponding solution is proposed. Application running on reconfigurable MPSoC consists of a number of tasks. Inter-task communication is the fundamental mechanism to ensure that the system works correctly. A simple but efficient mechanism for inter-task communication is proposed in this thesis. The mechanism provides a unified interface for communication over different types of tasks to ensure smooth communication between tasks. Based on the inter-task communication mechanism, a series of prototype systems are proposed. These prototype systems, which are both flexibility and scalability, provide supports to the research of reconfigurable MPSoC.