The Research On Hardware/Software Partitioning Algorithm With Different Constraints Based On Reconfigurable System On Chip

As a flexible, efficient and highly-reliable system, reconfigurable system-on-chipdesign has been widely accepted among designers since its debut. It has been appliedin designs which demands high flexibility and reliability. In particular, in actualscenarios where the system functions experience dynamic changes, flexibility andreliability are much more demanded. Thus, reconfigurable system-on-chip design haslarge potential to be applied in research on deep-sea and space exploration, nationaldefense and security, system encryption.In recent embedded system designs,hardware-software co design is usually adopted. Hence, it is vital to classify andcategorize the software and hardware of the system,It has become a hot research topiccurrently. Conducting in-depth research on the system structure, granular partitionsand concrete hardware/software partitioning algorithm, the author has mainly donethe following work:Firstly, the thesis has put forward a hardware model of reconfigurablesystem-on-chip design and designed different algorithm models regarding twodifferent hardware/software partitioning constraints. Establishment of models aredone on the basis of Direct Acyclic Graph (DAG), taking into consideration ofdifferent granular partitions and influencing factors on a case-by-case basis.Secondly, a hardware/software partitioning algorithm for reconfigurable systemwith area constraints has been proposed This algorithm combine greedy algorithm andsimulated annealing algorithm, the thesis constructs a mixed algorithm placing dualemphasis on hardware acceleration per unit area and communication time. Usingacceleration per unit area as the screening criteria of greedy algorithm, the mixedalgorithm is more scientific and rational. The time spent on communication is moreclose to the real in hardware/software partitioning of fine grain. The experiments haveshown that compared with greedy algorithm and simulated annealing algorithm, themixed algorithm can yield higher performance when the algorithm has increased nocomplexity.Thirdly, a hardware/software partitioning algorithm for reconfigurable systemwith time constraints has been proposed. the coarse grain has adopted to classify.Directed acyclic graph of a non-tree structure has been combined and transformed intotree structure. For the tree structure mentioned in the paper, dynamic programming has been planned in order to seek optimal solution for reconfigurable system withtime constraints.On the above three aspects,the prototype system has been builded which can beapplied to verify the algorithm. The performance and feasibility of the algorithm canbe verified in the specific design process.