LDPC Technology Research And Applications In Broadband Mobile Communications

Recently, the 4th generation (4G) of mobile communication system has received wide attention in the world. China also launched the "FuTURE" and "Gbps" program for the research on the key technologies of 4G Low-Density Parity-Check (LDPC) codes is a hot candidate channel code technology in 4G systems. LDPC has very attractive properties:error performance approaching Shannon limits, easy description and implementation, convenient theoretical analysis and research, easily decoded in complete parallel ways and suitable for hardware implementation. This thesis focuses on the LDPC decoder design in mobile communications system.The research concerns in this thesis are as follows:Based on theoretical analysis of Belief Propagation (BP) and Log-Likelihood-Ratio Belief Propagation (LLR BP) decoding algorithms, Uniformly Most powerful(UMP)BP_based decoding algorithm for structured LDPC codes is discussed with consideration of hardware implementation in 4G systems. UMP BP_based decoding algorithm can achieve performance which is very close to the BP algorithm's performance, while the computational complexity and memory requirement are greatly reduced. Besides, in UMP BP_based decoding algorithm the convergence property as layered BP decoding algorithm is remained. So UMP BP_based decoding algorithm is an advanced algorithm that can offer trade-offs between performance and complexity.Then Low-density high-speed reconfigurable decoding architectures are proposed with the field programmable gate array (FPGA) implementation of irregular structured low density parity check (LDPC) codes. The enhanced semi-parallel decoding architectures are easily scalable and reconfigurable for different block sizes. Based on the UMP BP-Based (Uniformly Most Powerful Belief-Propagation-Based) algorithm, this thesis optimizes the common components of parallel decoder structure for two different code words at the same time. Thus, the throughout of the decoder is increased. The FPGA implementation results on Xilinx FPGA Virtex-5 SX95T show that the irregular LDPC encoder can achieve a maximum (source data) decoding throughput of 344.9 Mbps at 18 iterations.LDPC has wide application foreground. This paper studies the LDPC decoder in OFDM system. Hopefully, it is beneficial to the further research work.