The Decoding Hardware Implementation Of Low Density Parity Check Code

LDPC code(Low Density Parity Check Code)is a powerful error correcting technique.Mackay and Neal prove that the performance of LDPC codes is close to the Shannon limits .Its decoding complexity is also lower than turbo code. Recently, LDPC code has drawn the worldwide attentions successfully because of its excellent performace and its bright application prospect in optic communications, satellite communications, deep space communication,the fourth generation mobile communication system ,digital subscriber loop with high speed or hypervelocity, optical and magnetic recording system, many companies are urgent to develop LDPC decoder on hardware.This paper firstly introduces the definition of LDPC codes, the basic construction of LDPC codes and the way of encoding,they are the foundations of decoding Secondly, we discuss the Belief Propagation (BP) algorithm and the Log-BP algorithm and simulate the Log-BP algorithm.The Log-BP algorithm is suitable for the implementation of the hardware decoder.Thirdly, given the decoding precision and the limit hardware resources,we discuss the selection of digital bit, and we offer the most suitable option. Fourthly,this thesis uses Verilog Hardware Description Language and adopts part parallel decoding configuration. We use the idea of top-down design to program the decoder with Verilog Hardware Description Language. Moreover, we synthesize and analyze the static time of the design with ModelSim and ISE to verify the correctness and the function.At last, we use the FPGA and relative hardware cells to design a decding board.