Design And Implemention Of LDPC Encoder And Decoder On FPGA Platform

The huge development of mobile communication technology has changed and curved people’s life.The complicated communication environment and higher requirement of people’s communication need is challenging the new communication system. The channel coding technology can improve the performance of communication system dramaticly and increase its capacity. For the communication system with high-throughput and low-latency,low-density parity-check codes(LDPC) are the excellent candidate. The design and implementation of low-density parity-check codes(LDPC) encoder and decoder has high engineering value in the high-speed communication system,especially the encoder and decoder with Gbps level throughput.This thesis firstly introduces the basic conception and structure of low-density parity-check codes(LDPC) and focuses on the study of quasi-cyclic low-density parity-check codes(QC-LDPC). According to the characteristic of low-density parity-check codes(LDPC), the advantage and application prospect is discussed. In order to meet the requirement of the given project,the encoding algorithms are discussed with the engineering prospect. And the Efficient algorithm is selected as the candidate in the standard of worldwide interoperability for microwave access(WiMax),because encoder using this algorithm has less encoding complexity and higher encoding speed.In order to design the decoder with high-throughput,the decoding algorithms and application structures are both researched.Among the various decoding algorithms,the offset min-sum algorithm is selected for its good decoding performance and reasonable application complexity.Then several critical parameters such as the maximum iteration time, the offset parameter and the quantization method, are simulated on the Matlab platform. Besides the algorithm,the implementation structured is also discussed in detail. Serial structure, parallel structure and partially parallel structure are compared both in the prospects of the decoding speed and the resource consumption. The parallel structure is the choosen one because it can be flexible between these two prospects. In the design, ping-pong operation and pipeline structure is adopted so that it can finish two codes decoding in the same time which impoves the throughput of the single decoder.The thesis has made a complementation of the low-density parity-check codes(LDPC) encoder and decoder on the XC7VX690 T of Xilinx. The length of the give code in 802.16 e standard is 2304,the rate is three-fourths. The maximum frequency of the system is 184.4MHz and the throughput of encoder and the single decoder is 8.14 Gbps and 358 Mbps.