Research Of LDPC Coding And Development On Hardware

Shannon developed famous interrupted channel coding theory in 1948．Under Shannon theory, more and more channel coding method which are close to Shannon limited are developed and used now. From old method such as BCH coding, Algebra code, RS code and convolutional coding to Turbo coding and LDPC(low density parity check codes) coding , the capability is get close to shannon limited.Low-Density Parity-Check (LDPC) Codes are a class of channelcodes based on graphs and iterative decoding whose performance is veryclose to the Shannon limit with low complexity and have strong errorcontrol strength. In this dissertation, the theory, design and application ofLDPC codes are studied, which involves block codes principles, codestructure, decoding, construction of sparse parity-check matrix, densityevolution and applications of LDPC codes. This article provide methodsto develop it based on FPGA. The main works and innovations are asfollows:1 . The fundamentals of information theory, channel coding and thedevelopment from theory to practice of channel coding are generated.And the introduction of Shannon channel coding theory and channelcoding methods closed to Shannon limited, especially the develop ofLDPC coding.2．The structure of LDPC codes is studied. Based on the matrix representation,Tanner, degree distribution of LDPC codes, the parameters of irregular and regular codes are defined.3．Research the construction of low desity patity matrix from LDPC codes,including irregular and regular codes.This article introduce Gallager ,BIBD and Mackay methods and also irregular method. According to partice, it also introduces several practical methods, such as sub-triangle method, rotationalπmethod and unit matrix method.4．The decoding of LDPC codes is studied. Hard desition decoding is studied. Based on the probability domain and the log likelihood ratio domain of BP decoding of LDPC codes, the modified BP decoding algorithms are paid more attention to, including the APP, UMP BP-Based, APP-B asedalgorithms.5．According to practical work, the develop of LDPC coding and LLR evaluation in decoding using FPGA are introduced. The structure of practical matrix and how to make it to FPGA chip are shown and Modelsim simulation.