Study On Implementation Of A Class Of Low-Density Parity-Check Code Based On FPGA

LDPC code(Low-Denstiy Parity-Check Code) is a powerful error correcting technique that is a good code near Shannon limit performance invented by Gallager nearly 40 years ago. Thanks to its excellent performace and its bright application prospect such as optic communications, satellite communications, deep space communication, the fourth generation mobile communication system, digital subscriber loop with high speed or hypervelocity, optical and magnetic recording system, LDPC code is widely considered as next-generation error-correcting code for telecommunication and magnetic storage, which is put a high premium on by academic circle and IT circle. And LDPC code has been the most spectacular spot in error-correcting coding area. It's clear that LDPC code will displace Turbo code in the near future. The academic significance and commercial value of study on LDPC, also the impulse on associated technology in IT area are great. LDPC code can be effectively decoded using BP algorithm.Since the direct implementation of BP algorithm will result in high hardware complexity due to a large number of multiplications, we may introduce some logarithmic quantities to convert these multiplications into additions, which leads to the Log-BP algorithm. In fact, both BP and Log-BP algorithm act on the same decoding rule.This paper focused on the study on LDPC code and its corresponding decoding algorithm. After that, for easy implementation, this paper bring forward a class of LDPC systematic code, and then advance its encoder and decoder architecture upon Log-BP algorithm. We fulfill the FPGA implementation of LDPC code encoder and decoder before this paper.In chapter 1, channel encoding's development , the place of LDPC code in channel encoding, also some study on LDPC code are introduced, and then, some FPGA design ways are discussed.In chapter 2, some fundamental knowledge about LDPC codes including the konwledge of block codes are introduced, also the Log-BP algorithm of LDPC decoder which determins the architecture of LDPC decoder is discussed.In chapter 3, the design and FPGA implementation of the LDPC code are discussed in detail, which is the topic of this paper. According to the Log-BP algorithm, the corresponding partly parallel decoding architecture is brought out, andthen all functional moduls are discussed in detail. The author illuminates the following issues emphatically: The partly parallel architecture of LDPC decoder Soft-decision decoding rule The quantization scheme of the intrinsic information(or channel information) and the extrinsic information The FPGA implementation of all the functional moduls of the LDPC decoder In chapter 4, the author makes an introduction of the simulation result byQuartusII and hardware test by downloading to circuit board. And the author introduces the design scheme of the corresponding encoder, by comparing the parallel encoding architecture and the serial encoding architecture, the author thinks that the serial one can match the partly parallel decoding architecture in throughput capacity.In the past, the theory and the performance of LDPC codes have be introduced much, but the implementation of it is so little. As more and more discussions of LDPC codes, especially of its hardware implementation, LDPC codes will replace Turbo codes in the near future.