ARM9 Core Backend Physical Design Based On 65nm Manufacturing Process

With more and more applications of embedded system in SoC design, ARM core based on advanced manufacturing process has been widely used and studied thanks to its high performance and low cost. So developping an ARM core with high market value is very meaningful.This paper is studied with the background of mobile applications, backend physical design of an ARM9 core based on 65nm manufacturing process is implemented. There are 5 major design steps, DFT, Floorplan, Physical Synthesis, STA/SI, DFM/DFY. In the DFT part, Scan and Mbist circuits will be inserted and verified, the cost of DFT circuit is only 7%. In Floorplan part, ARM9 core physical size of 1100um*1200um is decided with the consideration of area/power/SI etc. In Physical Synthesis part, good timing results of 400MHz are achieved, multiple-VT libraries are also used to optimize the leakage power. In STA/SI part, in-chip and off-chip ways are used to prevent the crosstalk noise and timing issue, the noise level is controlled under 0.36V. In DFM/DFY part, methods such as via optimize and CAA are implemented to improve yield of ARM9 core, CAA alone could bring yield higher about 0.39%. Some comparison about the 65nm ARM core with 90nm ARM core will be done in this paper too, so the benefits of 65nm process are revealed, include 27.43% area reduction and 37.5% increase of speed.The ARM9 core designed in this paper has high performance thanks to the advanced manufacturing technology and well organized design flow, include the frequency up to 400MHz and power consumption of only 301mw.