Simulation And Testing For HCI Effects In 65nm NMOSFET

The feature size of the device is becoming smaller in the putulity of the Moore 's law,with the consequent reliability problems affecting the lifetime of the device and the circuit.HCI degradation is an important reliability problem in the current ultra-deep submicron devices.In this paper,the HCI effect of 65 nm NMOS device is simulated and tested.The main research contents and results of this paper are as follows:Firstly,this paper describes the classification and damage mechanism of the hot carrier effect under the stress bias,and the causes of HCI degradation are changed due to different gate voltage.At the same time,this paper also introduces the classic hot carrier model "lucky electron model",which is widely used in the industry.This model holds that the hot carrier is lucky enough to get enough energy to get over the barrier and inject it into the gate oxide layer,causing the damage of the device.However,in the short channel devices,the lucky electronic model can not explain the HCI degradation at lower voltages.This paper introduces the "energy-driven model" to explain the hot carrier effect in this short channel device.Secondly,this paper gives the key parameters influencing the performance of the circuit and gives the distribution of the threshold voltage.Through the artificial fluctuation of the process parameters,the initial threshold value of the device can fluctuate to the position of no more than 1.5?,which is 414 m V±28.4m V,and then analyze the different degradation of the device after HCI stress in the case of these artificial fluctuations,namely the change of lifetime.The simulation results show that in the Halo process,the implant energy fluctuation is more obvious than the implant angle and dose,and the degradation is more serious.In LDD process,the effect of implant dose fluctuation is far greater than that of implanted energy fluctuation.In contrast to the LDD process and Halo process,the effect of implant energy fluctuation in Halo is greater than the effect of implant dose fluctuation in LDD.Finally,this paper designs the test structure layout and carries on the flow film.The accelerated stress experiment of 65 nm NMOS device was carried out through appropriate experimental procedure.The experiment found that the saturated drain current of the device,the transconductance of the linear zone,the threshold voltage,all had different levels of deterioration.In this paper,the comparison of the devices with different length and W/L of the three groups is obtained,with the decrease of the size of device,the device of hot carrier effect is more serious.In the research of antenna effects,the effect and reason of antenna structure on the hot carrier effect are given compared with the degree of degradation of different antenna ratio devices.According to the life expectancy acceleration model,the lifetime prediction of NMOS devices is obtained,and the hot carrier lifetime of NMOS devices is obtained in the SMIC standard 65 nm process.