Back-end Physical Design Of A Low Power WCDMA Module Based On 28nm Manufacturing Process

In recent years,the market for mobile electronic devices has become increasingly demanding.Not only high performance but also low power consumption is required.Power consumption along with performance has become a competition point in the mobile chip market.IC design for low power becomes increasingly important.With the increase of design scale and continuous decreasing of CMOS feature size,the power density is more serious.It brings enormous challenges for low power IC design.Therefore,in any step of IC design,both front-end and back-end,how to achieve low power design has become a problem that designers must face.This topic comes from the research and development project of a low power multi-mode smartphone chip in the enterprise.Based on 28 nm manufacturing process,the back-end physical design from netlist to GDSII of the low power WCDMA communication module in the chip is completed.The main research work of this paper is as follows:First of all,the main power source of digital IC is studied.According to the different hierarchies of IC design,power optimization methods are analyzed.Then some low power design techniques are mainly studied,such as clock gating,multi-threshold logic,multi-supply voltage,power shutoff,dynamic voltage and frequency scaling,adaptive voltage scaling and substrate biasing.Secondly,the whole physical design of the WCDMA communication module is carried out.By assessing the 9Track library and 7Track library,the 7Track library with lower power consumption is selected.Then by the Cadence P&R tool Innovus,floorplan,power plan,placement,clock tree synthesis and routing of the WCDMA module based on Common Power Format(CPF)are completed.On this basis,static timing analysis by Synopsys Prime Time and physical verification by Menter Calibre are done.With the requirements of low power,in the above physical design flow,different strategies of clock tree synthesis are experimented.By experiments,the author compares their effects to power consumption.Three different flows by Cadence latest clock tree synthesis engine CCOpt and traditional CTS flow are contrasted.Then the ccopt_ckspec flow under CCOptengine is identified as the CTS flow in this design.On the basis,to further optimize the clock tree,the parameter settings in the clock specification are refined.At last,according to multi-threshold logic technology,by swapping standard cells on the non-critical paths through Prime Time,the work of power optimization is completed.The final analytical results show: 1)For this WCDMA module,dynamic voltage drops,static voltage drops,electromigration and power-up time of power switches can meet the design requirements;2)UHVT standard cell ratio in the WCDMA module reaches 84.57%,which is a 15.18% increase over the original one;3)Compared with the former one,the leakage power consumption of the WCDMA module is reduced by 15.24%;4)The power consumption of the WCDMA module is 102 m W,which is reduced by 25.67% than the WCDMA module under the same process of the previous project.The low power WCDMA communication module in this project can meet the sign-off standard.It can provide some reference for low power physical design engineers.