Design Of Radio-Frequency Low Noise Amplifier Base On DECT Wireless Access System

With the rapid development of the wireless communications and its broad-based application, the demand of the wireless receiver is becoming higher and higher, and the radio frequency integrated circuit (RFIC) which based on CMOS (complementary metal oxide semiconductor) has a broad market and development prospects. The miniaturization, low-power, low cost and high performance of the wireless terminal system has become a trend. CMOS technology was into the mainstream of the world's technology industry with its characteristics of the low cost, low power and highly integrated. For multi-level cascade system, the first-class noise performance is the greatest effect to the whole system, and the low-noise amplifier (LNA) as the key modules of the wireless communication system receiver front-end RF, its performance plays an important role in the RF performance of the system. Therefore, this paper completed an amplifier design with the low voltage, low power, and low noise which can work in 1.9GHz DECT wireless access system based on requirements of the wireless communication systemIn this paper, first of all, it introduces the system theory of the wireless DECT and the two major performance indicators of the Low noise amplifier—noise and the nature of the linearity, and stress on analyzing the system structure of the radio frequency front-end in a super heterodyne receiver, the performance indicators of the Low noise amplifier for DECT wireless receiving system and the characteristics of the two ports network noise and cascading systems with linear and the noise. Then it puts forward the design specifications of the lose-noise amplifier; makes comparative analysis of the traditional low-noise amplifier topology properties, and puts forward a kind of non-linear compensation techniques folded cascode LNA based on the low-noise amplifier of the low-voltage low-power classical folded cascode structure. At last, it makes an analysis and optimization around low power consumption, noise and characteristics of the linearity. With the constraints of the low power and on the first stage of the noise figure that have a main impact on the low-noise amplifier, which achieves the optimal noise figure; At the post-stage of the characteristics of linearity that have a main impact of low-noise amplifier, which achieves the optimal of the linearity by using the technology of the PMOS transistors with non-linear compensation. Finally, it solves the problem of the conflicts that constraints each other among the three factors of the noise factor, power consumption and linearity.In this paper, it takes the TSMC 0.18μm CMOS process model by the design and simulation of the ADS2008, and compares it to the simulation results of the classic structure of folded cascode low noise amplifier to make comparative analysis. The results show that in accordance with the method that designed in this paper, the low-noise amplifier with the characteristics of the low power consumption, low noise figure and high linearity; and the optimization results of the noise and linearity are completely consistent with the theoretical. The LNA can meet the input and output impedance matching at 0.9V operating voltage, at the same time, the gain is 17.31dB, noise figure isl.19dB, input third order intercept point IIP3 as 9.35dBm and power consumption is only 6.8mW. Furthermore, it has good stability at the center frequency of 1.9GHz on the work of the band. Therefore, the circuit can be applied to the center frequency at 1.9GHz for DECT wireless access systems.