The Study And Design Of 5.6GHz CMOS LNA

With the astonishing development of the wireless communications, the high performance systems are greatly demanded, and the specifications for RF (radio frequency) and communication IC become higher and higher. Therefore, it is valuable to research and design RF transceiver circuitWith the continuous development of CMOS technology, CMOS RFIC technology with high integration can be comparable with traditional RF bipolar or GaAs technology nowadays. High quality RF CMOS module design research has become a hot spot currently. Meanwhile, practical requirement of low power consumption must be taken into account by LNA designers in order to improve portable performance of the product. Thus analog circuit octagonal rule should be complied during LNA design. Parameters tradeoff and overall optimization should also be achieved.The LNA (low noise amplifier) is one of the critical components in the RF transmitter and receiver. Its main function is the amplification, mixing and filtering for the weak signal from the RF receiver antenna or filter to get the intermediate frequency signal used in the back-end circuits of RF receiver. As the first stage of the system, its gain, NF (noise figure) and linearity directly affect the performance of the whole circuits.This thesis focuses on the design of 5.6GHz CMOS LNA. Starts with the research of device characteristic of 90nm CMOS process, The thesis discusses some normal devices'characteristics at high frequency. Basing on this we analyze the noise models of these devices, giving the method to optimize the noise performance under power consumption and impedance matching conditions. For the design of high quality factor inductor is important to design a good performance LNA, we analyze the structure and model of integrated planar spiral inductor of 90nm CMOS process, and get the quality factor and the value of the inductor with the help of Eldo tools, which of these are significant for the design of on-chip planar spiral inductors. This paper reviews and analyzes a low-noise amplifier (LNA) design circuits applied to the cascade topology based on RF CMOS technology. The low noise amplifier was implemented in TSMC 90nm low power RF CMOS technology. The simulation results show that the is 18.5 dB, the noise figure is 1.78dB, and 1dB compression is-21.72dBm, anⅡP3 of-11.75dBm,and the power dissipation is below 25mW from a 1.2V supply at 5.6GHz.