Design Of Low-Voltage, Low-Power CMOS Radio-Frequency Low-Noise Amplifiers

With the development of radio frequency (RF) communications and the CMOStechnology, it has become a reasonable choice to implement the RF communicationcircuits and systems in CMOS process. The RF front-end circuits in this kind ofmixed-signal systems are required to be able to work under low voltage. Front-ends,especially LNAs for modern RF communications are also required to be low-noiseand highly linear and to fulfill those requirements with low power is among the keytechnologies for the implementation of RF communication systems.The design of low-voltage, low-power CMOS low noise amplifiers (LNA) isconducted in this thesis and includes:1. A simple design model and the method to extract its parameters by circuitsimulation and data fitting is proposed based on simplifying the circuit simulationmodel of short channel MOSFET in a specific operation region (strong inversion andsaturation). The large-and small-signal model, and noise model can be derived toanalyze the gain, noise, linearity and power of inductively source-degenerated CMOSLNAs and to predict their simulation results so that the design iterations can bereduced.2. The contribution of different noise components of MOSFETs in 0.18micrometer process to the noise figure (NF) of the inductively source-degeneratedLNA is calculated and the analytical expression of the NF is derived. It is shown thatdue to the parasitic capacitance NF is still dominated by the channel thermal noisecurrent;therefore, low noise can be achieved with low power dissipation by properlysizing the MOSFET in the input transconductance stage. A low-voltage foldedcascode inductively degenerated LNA is designed and the above analysis is verifiedby simulation.3. The nonlinearity of the inductively source-degenerated LNA is analyzed withseries expansion method and analytical expressions relating the power and linearity tothe size and bias of the MOSFET are found. Compensation is needed to achieve highlinearity, and different compensation methods are compared. A low-voltage foldedcascode LNA compensated using MOSFET in the triode region is proposed, and thenthe design guides are given. About 5dB input-inferred third-order interception pointpower enhancement at little power cost has been demonstrated by the measurementsof the fabricated IC chip compensated with this technique and designed under thegiven guides.4. The effects of packaging parasitics on the performance of inductivelydegenerated LNAs are analytically studied. It is shown that, with parasitics given, toachieve perfect input matching, high gain and low noise, the capacitance across thegate and source of MOSFET in the input stage should be properly large. Two ways toenlarge the capacitance are compared and using longer channel MOSFET ispreferable to adding an extra parallel capacitor. These observations are verifiedthrough circuit simulation.