Design And Optimization Of CMOS Low Noise Amplifier

As the first active block of the wireless receiver, the performance of LNA(Low noise amplifier) has a significant impact on the entire wireless communication system. Therefore, the research of design and optimization of CMOS LNA is a valuable work. The main contributions of this paper are as follows:1. We analyzed the impact of Miller effect on the LNA. The influence of gate-drain capacitance of a transistor on input impedance and frequency response of an amplifier is usually called Miller effect. However, most of the papers ignored the effect of gate-drain capacitance due to its complexity when analyzing a CMOS low noise amplifier (LNA). This paper decomposed the gate-drain capacitance into the input and output nodes according to Feedback Decomposition Theorem (FDT), and then analyzed the small signal equivalent circuit based on Thevenin's Theorem. For the first time, revised LNA signal equivalent model was developed.2. We carried out a detailed study on the performances of LNA based on the revised LNA signal equivalent model, including input impedance, noise figure, output impedance, power gain, linearity, stability, power dissipation, etc. Then the corresponding revised performance formulas were developed.3. By setting power dissipation and power gain performance specifications of LNA as design constraints, We present an geometric programming (GP)-based global optimization method of CMOS low noise amplifier (LNA), which is based on the revised formulas of LNA. Simulation results showed that, the revised formulas were more accurate in the description of input impedance and noise figure performances of CMOS low noise amplifier. Compared with existing designs, the proposed 2.4GHz LNA based on the revised formulas had lower power dissipation and better noise factor.4. We present a geometric programming (GP)-based optimization method of fully integrated CMOS LNA. With a lower quality factor, the parasitic resistance noise of the integrated gate inductor can not be ignored compared with the noise of MOSFET. By setting the noise figure, which contained transistor noise and parasitic resistance noise, as optimization objective, we made a good compromise between the transistor noise and parasitic resistance noise in the integrated gate inductor. 5. After making a analysis and comparison on the existence VGLNA(Variable gain low noise amplifier), we present an VGLNA circuits, which power gain were variable and had a fine input & output impedance, noise figure, power gain, stability performances. The design has been sent to fabricate in TSMC 0.18um CMOS process.