Full Differential SHA Design For High Speed Pipeline A/D Converter

Being a key functional block of high speed high precision analog to digital converters, Sample and Hold Amplifier(SHA) is being studied a lot in both school and industry. Pipeline ADC is widely used because of it's superior trade off among speed, area and power. As Sample and Hold(S/H) lies in the front end of pipeline ADC, its speed and accuracy dominant the performances of whole system. Based on ASMC 0.35um 3.3v process, S/H for a 12 bit 100MHz pipeline ADC was designed.The paper studied structure of pipeline ADC, theory and operation of S/H, as well as the requirements of S/H for pipeline ADC. The paper also analyzed the error sources of S/H in both sample and hold phase, offering proper solutions. Then a detailed analysis of the performance of op-amps was given, followed by a detailed design process for capacitor flip around S/H. The circuits design covered: gain boosted telescopic op-amp, common mode feedback circuit, non-overlap clock generator and bootstrapped switch. The care focus on gain boosted op-amp and bootstrapped switch. Simulation was done to clarify the circuit performance.