Design And Realization Of High-Speed Real-time Massive Data Acquisition System

With the development of information technology, communications, radar and other fields place higher demand on high-speed, high-capacity and real-time data acquisition. In the actual test application, there are a number of data acquisition process requires a long time, high-volume data handling capacity, requiring real-time data collection and save. Compared with traditional data acquisition system, this high-speed and massive data acquisition system doesn't need the control of CPU command, but operates by full hardware based on FPGA. Therefore, it has high reliability because that it can high-speed and real-time acquise and save some data continuously and uninterruptedly, but not be influenced by bus bandwidth and other applications running.The main researches of this thesis are as follows:1. Study the necessity and the major significance of high-speed data acquisition system, and analyze the domestic and international high-speed data acquisition system research. According to the the diffculty in performance indicators, cross-clock domain data transmission, and complex timing control of SDRAM, put forward the design that FPGA control the timing of system.2. Analyze the working principle of DPRAM and SDRAM.As the design require higher clock frequency of and the logic of rich resources, Xilinx's Virtex-4 family of FPGA chip is choiced.Design the hardware structure that FPGA control DPRAM cache and FPGA and DSP time sharing read and write SDRAM to meet the requirements of high-speed continuous uninterrupted flow data storage.3. According to the system design, calculate sampling frequency by band-pass sampling theorem;design the state transfer process of the SDRAM controller;VHDL language is used to achieve a SDRAM controller, two DPRAMs and their controllers, as well as the modular design of the interface between FPGA and DSP.And VHDL codes, logical schematics and Modelsim wave simulation of the main modules are given.4. This issue fulfills the requirements for a long time, high-volume data handling capacity and real-time data collection and real-time save during the data collection process by the design. The data are proved correct by the DSP testing of SDRAM memory data.The design realizes high-speed and real-time and massive data acquisition system by FPGA successfully.