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The Design Of High-speed Real-time Data Acquisition And Storage System Based On FPGA

Posted on:2013-04-30Degree:MasterType:Thesis
Country:ChinaCandidate:L ZhaoFull Text:PDF
GTID:2248330374952822Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of modern technology, such as the field of wireless communications, image processing, and nuclear magnetic resonance spectrometer, and all need the high-speed transmission of large amounts of data between devices at all levels. Therefore need to be using high capacity, high speed system design of storage media.As science and technology, people began to use memory, memory products are constantly evolving, from the first DRAM has been developed to be used in this paper to DDR3SDRAM. In termsof timing control, the FPGA chip with higher clock frequency and hardware resources canbe quickly and effectively control complex combinatorial logic and sequential logic circuits. So,through a combination of FPGA and DDR3SDRAM interface design, in the acquisition of large capacity and high-speed storage played a central control system.Based on the background,in-depth reading and understanding of the control principle of the FPGA development process and DDR3SDRAM, knowledge of storage structures, interfaces, timing, etc. In this paper, based on Xilinx’s Spartan6the FPGA as a storage medium as the control core, Micron DDR3SDRAMand high-speed acquisition and storage system for data transmission via a USB2.0system to meet modern industrial and scientific research in high-speed, real-time data acquisition and storage requirements.This paper first describes the technical background of the high-speed acquisition and storage system and development at home and abroad, and the system for the existinguse DDR or DDR2memory, DDR3memory faster read and write data and programswith greater storage capacity. Second, given the overall structures of the systemarchitecture and design of their thesis ideas, namely, how to implement FPGA-basedcontrol of DDR3controller, and established the composition of the various modules in thecontroller system. Then the ISE12.4development platform and Verilog HDL design entryway, and a combination of open source IP core resources, carried out a detailed logicalanalysis and design of each module. Finally, the hardware environment to test the systemdesign, analysis of the consumption of system resources, real time and to use chipscopelogic analyzer tools of the system functional verification.Validation result description, acquisition and storage system based on FPGA with DDR3, and read and write rates of data throughput than the existing system has a lot of promotion, meet the requirements of the initial system design. Stable operation of continuous and prolonged electrical work, no error generationed.
Keywords/Search Tags:FPGA, DDR3SDRAM, FIFO, Verilog HDL, High-speed acquisition andstorage
PDF Full Text Request
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