Key Technology Research Of High-speed Data Acquisition System In Time-of-flight Mass Spectrometer

Time-of-flight mass spectrometer (TOF-MS) compares other mass spectrometers to have good sensitivity, high resolution, quick analysis speed, mass detection upper limit only receives ion detector limit. It is the most promising mass spectrometer now.At present, TOF-MS has been used in studying many international most fronts the hot topics, it is the unreplaceable powerful tool domaining in gene and genomics, protein and proteomics, biochemistry, medicine and virology, for example peptide and protein analysis, bacterium analysis, medicine decomposition research as well as viral examination. Specially in the biological macromolecule analysis that needing the great flux and the quitckly analysis speed, TOF-MS becomes the most important analysis method.From TOF-MS own characteristic, the principle and the technical angle generalized analyzing and comparing the TOF-MS two kind of detectors (ADC and TDC), obtains ADC TOF-MS to be possible to enhance the dynamirange, the quality precision and the mass resolution, in the biochemistry analysis research, using high speed ADC TOF-MS to analyze is the main development direction. At present, some overseas big companies (for example Agilent Technologies,SHIMADZU and so on) already produced ADC TOF-MS, but didn't have related literature on the report to its research technique. The home does not have the independent research and development the high speed ADC data acquisition system being able to satisfy TOF-MS. Therefore it is significant to research and develope the high speed ADC data acquisition system in TOF-MS.This subject derive from the topic of the Key Technologies R&D Program of the National S&T Program in the 11th Five-year Plan in China, "Two Ion Mass spectrometer Core technologies And Key component Research And Development", the high speed ADC data acquisition system is one of key components, its performance quality influence mass spectrum peak resolution, sensitivity, dynamirange, quality circle and so on important technical specification. This topic main research: High speed ADC and the peripheral circuit design simulation, the analysis Time-Interleaved ADC channel mismatch error, designs DDR2 SDRAM data storage and the USB2.0 data transmission, the FPGA internal data processing research. The technology in this topic has certain reference value to develop the high speed data gathering system in TOF-MS.In TOF-MS, flighting time of ions is extremely short, closes nanosecond level, belongs to the supervelocity data acquisition system. At present, acquisition time of the commercial TOF-MS approximately is 200us, therefore the data quantity is big, and the spectrogram of each time signal-to-noise ratio is big, these bring the challenge in this design. This design in according to the key technologies of system needs, modulates the system, studies the development one by one. This work contains three main contributions.First, a overall design of the high speed data gathering system in TOF-MS is proposed, this plan takes the system core by XC5VLX50T FPGA. The TOF-MS signal undergoes a series of transformations, signal enters signal modulate amplifier and it was enlarged 5 to 10 times, then changes the signal transforms to tally the ADC input signal through the single end to double-end transports, under the function of sampling clock, the analog signal changes to digital signal by the ADC. The signal transports to FPGA through the LVDS connection. In the FPGA carries on the data buffering and the serial parallel transformation, uses DDR2 SDRAM as the exterior memory of data processing, realizes data superimposition processing and digital filtering processing, finally transports data through USB2.0 data to PC machine. The control of system completes completely by FPGA.Next, the design of the high speed ADC and peripheral circuit was given, the core part of the data acquisition uses Atmel Corporation's AT84AD001B, this ADC is setted on 3-wire serial interface to work in interlaced mode, and this can achieves sampling rate the system needs.To guarantee that time resolution of overall system, the Pre-amplifier should have the good high-frequency response to guarantee it is not distorted enlargement to the fast change's mass spectrum signal. Because the ADC single channel sampling rate is 1Gsps, the double channel sampling rate is 2Gsps, according to the Naikuisite sampling law, we preliminary suggest -3dB band width of the Pre-amplifier is not lower than 300MHz, namely the rising time of the amplifier maintains about 2.0ns. the Pre-amplifier to use two level of enlargement structures was Designed, first level of AD8099 is five times of enlargements (may through resistance adjustment enlargement factor), the second level of AD8031 amplifier for the fixed 2 times of enlargements, simultaneously outputs for the difference signal. The design of Pre-amplifier should reduce the noise which oneself brings as far as possible, simultaneously to satisfy the ADC double-end input, the Pre-amplifier has used the differential input. Finally the testing of the Pre-amplifier performance was given and the performance satisfies the design requirements.The sampling clock is the base element of A/D transfer network, along with the enhancement of the sampled signal speed, the frequency rapidly of sampling clock is also enhanced, it is getting more and more noticeable to the influence of high speed, the high accuracy ADC transformation performance by the clock jitter. The influence formula of ADC transformation performance by the clock jitter was given and the simulation mode of the pipelined ADC was established, joins the clock jitter in the clock to carry on the simulation, compares the obtaining signal between clock jitter and the ideal clock, thus obtains the influence of the clock jitter from the theory and the simulation to the ADC sampling.Time-Interleaved ADC (Time-Interleaved ADC, TIADC) has the channel mismatch errores, such as the offset error, the gain error and the time-skew error, which reduced system's signal-to-noise ratio seriously. The theoretical calculation two channel TIADC which uses in the system was given, and obtains the ADC output frequency spectrum formula containing three kinds of mismatch error. Further, the sampling model of the multichannel Time-Interleaved ADC was established, gives the multichannel mismatch error frequency spectrum formula. Finally the method of eliminating the channel error which is in connection with the channel mismatch error in the system was given.Finally, according to the TOF-MS principle, the model that was useing DDR2 SDRAM as the exterior memory of data processing, gathering many spectrograms to carry on the superimposition and digital filtering processing, then transporting data through the USB2.0 connection to computer was proposed, because of the great data quantity of the TOF-MS, low signal-to-noise ratio in the single measurement spectrogram. The design of DDR2 SDRAM based on Xilinx FPGA was given, and carried on the read-write test to the DDR2 design. The core part of the high speed data transmission chooses Cypress Corporation's CY7C68013A, the firmware program, the driver and the FPGA program were designed, through the test obtains transmission speed of the USB2.0 bus is 22MBytes/s, because after data superimposition processing, the data quantity reduces, after the computation, transmission speed of the USB2.0 could satisfy the request. At the finally of the article, analyzes data superimposition processing to be possible to reduce the data transmission speed, establishes the data superimposition the model, and finishes the simulation of the data superimposition and the digital filtering.