Design And Implementation Of High-speed Data Buffer Based On FPGA And DDR2-SDRAM

With quick development of information science, the demand of real-time signal processing task is becoming more and more significant, and the high performance request of data caching and processing has increased remarkably. FPGA (Field Programmable Gate Array) has the advantages of design agility, reconstruction and strong adaptability. Meantime, Double Data Rate2Synchronous Dynamic Random Access Memory (DDR2-SDRAM), as the latest generation memory, has the advantages of high speed, superiority of price and mass storage. Hence, this type of memory are widely used in research and development of high-speed data acquisition system in a variety of scientific and technological fields.The high-speed real-time data acquisition system based on FPGA and DDR2-SDRAM is designed and implemented in this thesis. This thesis focuses on the design of the DDR2-SDRAM controller. With top-down and modular design methods, the DDR2controller is split into a number of modules. And every module is achieved by using Verilog HDL. The design is simulated and verified under Modelsim6.6. The simulation results show that not only correct read and write data、 but also the speed of controller can up to24.96Gb/s when the work clock frequency is195Mhz, fully meet the functional requirement and real-time performance requirement of the system,apart from this,the delay of waveform is very small.In addition,as so fast the transmission is,the greatest advantage of the proposed technical solutions in this thesis is can applied to some aspects which need to fast and accurate real-time transmission of images.