A State Machine-Based Approach To Functional Verification About Digital Logic System

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design methodologies that are collectively referred to as reuse-based system-on-chip (SoC) design which partitions a system into several sub-function blocks that are always realized and obtained as intellectual property (IP) blocks from internal sources or third parties, and combined on a single chip to achieve the system function. With this design strategy more and more function blocks need be implemented as IP blocks, and the IP blocks are paying a more and more important role. If there is something wrong in IP blocks about their function, the whole design will fail undoubtedly. At modern system there are so many parts which need be implemented as digital logic blocks, so functional validity of implementation about digital logic system has becomes a key problem that attracts a lot of attention..A digital logic design begins in the mind's eye of the system architect(s) which is its original intent and intended behavior of the design. From the mind, it goes through many iterations of stepwise refinement until the layout file is ready for delivery to the foundry. At every level of refinement the design must be verified to make sure that it fits into the original intent. The goal of functional verification is to ensure that the design meets the function requirements as defined in the functional specification.There are many technologies that can be used in functional verification of digital logic system, such as simulation-based verification, formal verification and so on. With understanding of verification technologies mentioned above, we come to the conclusion that if we want to verify the design completely we must explore functionality and features completely. So a state machine-based approach is proposed which can extract functionality and features completely and verify the design completely. In this approach with theory of state machine-based function extraction the complete test vectors which is created for RTL implementation are created through FSM model built from functional specification of system, then those complete test vectors are used in the simulation-based verification to achieve the complete functional verification. In this paper, state machine modeling of the design that is described as requirement of system must be built using modeling tool (MATLAB/Stateflow) in the first place. Simulink that MATLAB provide can simulate the model to ensure it meets the requirement. And then completely functionality and features are extracted from the model of finite-state machine with state machine theory. Finally, verify digital logic design and prove the design meets the intent using simulation tool (ModelSim) through functionality and features extracted. Universal Asynchronous Receiver/Transmitter (UART) is commonly used in modern design. So in this paper, UART is taken for an example to show the feasibility and efficiency of the state machine-based functional verification approach.