Design And Verification Of IIC Bus Interface IP

With the development of semiconductor technics, the design of integrated circuit has entered into sub-micron era and chips with millions of transistors have become common. When the whole digital computer system can be integrated into one chip, SoC (System on Chip) has bcome an inevitable result of the current technology trend. As SoC presents a lot of advantages, it also puts forward new challenges to the design and verification of circuits.Reusable IP is considered a good solution to the complexity of SoC and the time pressure from market. Random-logic and finite-state-machine are two main description methods in IP design. On the other hand, the verification method based on transaction have been paid more and more attention. In this thesis, an integrated IIC Bus interface IP is designed based on random-logic according to IIC Bus's specification. Some functional verification methodologies are studied, and a complete testbench for the IIC Bus interface IP is constructed. Main works and achievements are as follows:Firstly, two design methods are compared, one is based on random-logic and the other is based on finite-state-machine, then an IIC bus interface IP with relatively full functions is designed based on random-logic.Secondly, under the guidance of the functional verification methodology which is based on IP reuse, a testbench of the IIC interface IP based on BFM is constructed with Verilog HDL.Finally, basic methods of functional verification and relevant development are studied. A testbench is established using a new Hardware Verification Language named "OpenVera" which is presented by Synopsys. The performance of the new testbench is compared with that of traditional methods. The results of the comparison indicate the new verification language and method improve the performance of functional verification.