The Design And Verification Of SPI Based On UVM

With the rapid development of the So C(System on Chip) and the widespread use of the IP(Intellectual Property), verification of the So C has become the bottleneck throughout the design process. Verification runs through the whole process of IC design. Effective verification not only ensures the correctness of the implementation, but also improves the design productivity, which is a guarantee to reduce the time to market. The So C verification can be divided into two parts: functional verification and sequential verification.The main subject of the study is the critical part of the So C verification-- digital functional verification.First, the current So C in the background, goal and signigicance is surveyed, showing the importance of verification in So C design.Besides, the difficulty of verification is learned.After analyzing and concluding the current mainstream verification techniques,the methods to improve verification efficiency are shown, which included Coverage Driven Verification, Constraint Random-Based Verification and Assertion Based Verification. The verification language System Verilog possesses many features, such as OOP(Object Oriented Programming) and constrained randomization, which providing strong support for functional verification. UVM provides a standard library which possesses a series of ports on the basis of System Verilog, making the rstablishmen of verification testbench easier.SPI is a serial periphery slave interface, and Si4432 is a radio freqency transceiver with high performance. This paper designs a SPI depend on the Si4432. After analyzing the SPI protocol, the principle, the basic structure, the working mode and the transmission mode of SPI are studied. Otherwise, a design of SPI is completed with Verilog HDL.The focus of this paper is verified the design of SPI. First, a key architection of testbench is summarized through the design of SPI. Then a testbench is designed and built in System Verilog based on this method with UVM. Finally, the testbench has optimized. Through the virtual interface, this testbench can configure registers at same time transmit the packet data.The scorebroad can receive data initiatively by using the form of FIFO to connect each component. In order to realize the completeness of the whole testbench, abnormal stimuli have added. The driver and monitor is improved through callback, which makes this testbench can be used in other designs and greatly improves the efficiency of the testbench.At the end of this paper, the functional coverage of the testbench is tested. The method which uses to generate the test stimulus can be adjusted by observing the functional coverage, so that the stimulus will be as complete as possible and both the code coverage and functional coverage will convergence as soon as possible, which ensure the correctness of the testbench and complete the verification of SPI.