The Study On Functional Verification Methods And Technologies For Sequential Circuits

In order to solve the problem that verification has became the bottleneck of IC design and system design industry, to avoid the high repair cost of finding faults in the design anaphase, and to find faults as soon as possible, the functional verification methods and technologies in the IC frontend design in this dissertation are researched. The dissertation takes the sequential circuit as studying object and uses many kinds of simulation verification coverage to analyze the great deal of experiment data, including code coverage, and functional coverage. Then two different verification methods——based state table and based state chart are compared, and fitting sequential circuit method is summarized.Verification method based state table and method based state chart are compared for the first time, and characteristics of two methods and fitting sequential circuit methods are summarized. Experiment approves that verification method based state chart exceeds the method based state table in simplicity, search arithmetic efficiency, testing sequence length, testing speed and validity. Because it is easy for automation, it more suits for large or middle scale circuits. On the other hand, the method based state table produces full-scan test vectors. Although it has simple principle, but it will has more and more test vector, till becomes the impossibility with increased of circuit scale, especially when cope with sequential circuit. So to the sequential circuit, the method based state chart is more suitable. In this dissertation, the evaluating scheme that functional coverage combined code coverage is adopted. The functional coverage checking method which assertion combined simulation is addressed in this dissertation. It clarifies simulation results and makes the simulation more observable. The conclusion shows that functional coverage combined code coverage provide an integrated quality verification gauge.