Research And Design Of The Memory Based On DSP Chip

On-chip memory is one of the main components of the DSPs. The high-speed and low-power memory will improve the performance and reduce the power of the DSP. How to optimize the performance and reduce the power of the memory is the key of the DSP.Based on the study of low-power design technology, this paper designs and optimizes the DARAM(Double Access RAM) of X-DSP in low power, respectively at system level and circuit level. Firstly, the memory is partitioned into several banks and the word lines are divided to reduce the load capacitance and then reduce theirs power. Secondly, by using the improved word line pulse technology, the clock signal is divided into multiple segments to decrease the amplificatory time of the sense amplifier and then to reduce its power. Finally, two level static decoding strategy is used to reduce the load capacitance and to lower the power of the driving word line. On the basis of above ideas, an 8Kb DARAM with the frequency of 100MHz is implemented by full-custom design method and fabricated in 0.25μm CMOS technology. This paper researches the design of the layout and its Starsim simulation of the layout. In typical case, the access time is 696.35ps, and the average power is 65.32mW at 2.5V. The system using our DARAM works well, meanwhile the performance and the power meet the design requirements.Another issue of this paper is the design and optimization of X-DSP Cache. To improve the efficiency of Cache, firstly this paper sortes the memory unit by a parity combination method so as to reduce the address line and speed up the response rate. Secondly, a replacement algorithm based on stack is adopted to accelerate the speed and improve the performance of Cache. Finally, a CAM structure is applied memory cells to improve the efficiency. On the basis of studying the architecture of Cache, this paper presents the whole design flow including logic, layout, simulation and testing design. As shown in the test of the layout simulation, the average power is 0.054mW at 100MHz. The system with our Cache works stably, meanwhile the performance and the power consumption meet the design requirements.