Noise Analysis And Design For Full-Custom & Semi-Custom Mixed Design Methodology

Continuous scaling of technologies towards deep submicron, even ultra-deep submicron will severely aggravate noise and other electrical problems, such as interconnect crosstalk, IR-drop, leakage current, and so on, which may lead to different kinds of unexpected behaviors including logic or functional failure of digital circuits. Since the impact of noise is becoming critical, it's important to study signal integrity in deep submicron IC design.The usage of noise sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more serious. This paper focuses on the capaci-tive coupling and its effects on dynamic node. The paper proposes a new leakage tolerant dynamic circuit style, Complementary Boost Logic (CBL), which highly improves domino's noise immunity and keeps high performance. A new circuit style improving the charge sharing noise of the high speed decoder logic in the cluster design is presented in this dissertation. To solve the long wire runs feeding domino gate inputs, we give an improved circuit, which efficiently increases the circuit's reliability.Today, we have to employ CAD tools to analysis signal integrity in the large scale circuits. For semi-custom design method, we can use PTSI or other tools to analyze the noise of gate-level netlist, and for full-custom design method, we can employ HSPICE to simulate small scale transistor-level netlist, whereas there are no EDA tools to support the signal integrity analysis for the full-custom & semi-custom mixed design method. We propose a new noise analyze flow, making use of existing EDA tools by characterizing full-custom functional module, which completely solves this problem. Finally, we compare the analysis result of a full-custom & semi-custom mixed designed four-bit address decoder with its HSPICE simulation result. The results prove this flow accurate and effective.