Full Custom Design And Verification Of Data Cache Tag

In modern microprocessors, Cache has becoming an absolutely neccessary function component. Its speed and size has been one of the main criterions to evaluate the performance of microprocessors. With the improvement of the processor's speed continuously, the study of how to design an Cache Tag in full custom mode provides more important signification, not only in theory, but also in practice.On the basis of deep research on Cache technology, this paper presents the logical, circuits and layout design of the Tag module in the data Cache of the X microprocessor,according to the system design requirement, whice makes sure that the X microprocessor can get the data from the data Cache in a cycle when hit.There are three flash features in the paper. The first one is the design of three separate tags to realize a 3-ported Tag, which respectly response to the requests of U pipeline, V pipeline and Snooping bus. These three tags work separately, but implement the 3-ported Tag's function together. The second one is a dynamic circuit designed for hit judgment, which reduce the comparing time sharply, and finally a totally new pseudo LRU mechanism is proposed, which not only effective, but also can be easily realized.On the system verification platform, the function simulation in system level about the pseudo LRU mechanism and MESI protocol is taken, and the results conform to the original intension of our design. Simultaneously, deeply SPICE simulation on the entire Tag design is applied, and we focus on the simulation and analysis of the hit judgment circuit.The outputs of the simulation show that, on the condition of 0.18μm CMOS technology, the access time is 1.13ns, the delay until the "hit" signal outputting effectively is just 1.49ns, which makes the X microprocessor can easily acquire a data from data Cache, just in a cycle ,when the working frequency is 250MHz.