Register File Design And Optimization In Multi-Threading Environment

How to exploit the parallelism of processor is an important direction to which the processor designers make great efforts. The traditional RISC processor architecture and compile optimizing technique was focus on exploiting the ILP, improving the IPC of processor through issuing multiple operations in one cycle. However, the finite ILP in single program determines that the resource utilization of multi-issue processor is low. So, multi-threading emerges as the times require.Multi-threading technique can improve the resource utilization of processor through using TLP, and achieve that the function units are shared among multi threads. Multi-threading processor execute the instruction flows from different threads, so that the long delay in single thread is hid very well, and the performance of processor is improved obviously. However, multiple threads run in parallel make a great challenge to register files.As a important component, an effectual design of the register file hold the balance for improving the performance of a microprocessor. Register file is also called register stack. Just like a small and fast buffer, it is used to store the operands and middle results. In the computer storage architecture, register file is set at the top layer, so the distance form it to CPU is the shortest and the pace to access it is the fast.A general register file which support multi-threading with high performance is designed in this thesis. There are 3 read ports and 2 write ports in the register file which support 4 threads running in parallel. At first, we researched the characteristics of the multi-threading architecture as well as the function and structures of register file, and analyzed the relation between process and register window. Then Aiming at the characteristic of the multi-threading environment, we make a particular design for the structure, function and realization of the register file. Register partition, overlap register window and hierarchy extension technologies were applied synthetically in the design and constructed"double layer register window"structure. At the point of realization view, we also researched the data coherence strategy management of the double layer register file, and present the ports description and timing design. Otherwise, we designed the management and control of the window exception particularly. At last, we presented the circuit design of the Active register file.With reasonable organization and effectual management strategy, this high performance register file satisfy the requirement of four threads running in parallel, and attains the expected goal of deign.