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Studies On Test Cost Reductions Using Scan Chain Disabling Technique

Posted on:2012-07-25Degree:MasterType:Thesis
Country:ChinaCandidate:P LiuFull Text:PDF
GTID:2248330374991081Subject:Software engineering
Abstract/Summary:PDF Full Text Request
Integrated circuits(IC) are widely used in daily life. IC testing gets more andmore attention as an important part of IC product quality assurance. However, ascomplexity and integration of the Circuit Under Test (CUT) are increasing, the testbecomes very difficult. The test cost is very high. Therefore, reducing test costs andkeeping low-power integrated circuit testing will become particularly important.Multiple scan chain test techniques have long been proposed and widely used, inwhich scan test scheme based on scan chain disabling technique is one of populartechnologies in current. Base on scan chain disabling technique, capture in turn scantest scheme is increased the chance of capture of the faults, and is reduced morepower.Scan chain disabling technique effectively reduces the test power, but needslonger test application timeļ¼Œso it increased the test costs. To solve this problem, thisthesis proposes a method for low cost testing based on scan chain disabling technique.To solve this problem, this thesis proposes a method for low cost testing based onscan chain disabling technique. The proposed method uses the compatibility betweentest vectors to reduce test application time. Its implementation process as follows. Thetest vectors which need to scan in the circuit under test, calculate the compatibility. Itcompresses the compatibility bit in the second half of previous test vector and firsthalf of later test vector, to achieve the reduction of scan into the scan chain in theamount of data. Experimental results show that the method can effectively reduce testapplication time, and no additional hardware cost.Secondly, we propose a scan chain reordering method based on capture in turnscan test scheme in this paper. This method capture the different scan unit of the samefailure, and then rearrange the scan unit to the different scan sub-chain, to increase theprobability of faults to capture. First construct a graph, in which the scan unit in thescan chain as the nodes, these nodes through which can detect failures will be acommon connection, the formation of an undirected graph. The number of faultsbetween scan units, which is used to work together to detect, is the connection weight.The connection weight is the number of faults between two scan units. The faults canbe detected by both of scan units. So the problem of increase the probability of faultsto capture can translate to the maximum cut problem of undirected graph. And use the greedy algorithm to solve this problem. Experimental results show that the methodcan effectively reduce the number of test vectors test, then reduce application time,and reduce the test power.
Keywords/Search Tags:full scan design, scan chain disabling, capture in turn scan test scheme, low cost test, low power testing
PDF Full Text Request
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