Design Of Key Cells In 12bits 40MSPS Pipelineadc

With the rapid development of communication and digital signal processing, analog-to-digital converter, as an interface between analog signal and digital signal, becomes more and more important. At the same time, pipeline ADC is widely applied because of a perfect tradeoff between speed and resolution. Based on SMIC 0.35?m CMOS mix signal process, the design of the key cells in a 12bits 40MSPS Pipeline ADC is completed, which can be used in video signal process, portable communication and CMOS graphics sensor.This paper describes the design of high speed and resolution pipeline ADC,focusing on the design of some key cells. Kinds of non-ideal factors and error sources in the pipeline ADC are analyzed. RSD is used in 1.5-bit per-stage digital output pipeline ADC. The circuit includes a capacitor flip-around sample-and-hold cell that gains high speed front-end sampling. The bottom plate sampling technique is employed, which could not only decrease the charge injection error but also eliminate the effect of clock feed-through. A bootstrapped switch is designed to make the linearity better. A folded cascade operational transconductance amplifier with gain-booster auxiliary circuit is adopted to enhance the speed and precision performance. Dynamic comparator is also used to lower the power dissipation. Based on charge transfer pipeline ADC, MDAC of 1.5-bit per-stage is designed.All the blocks above are simulated with Cadence Spectre and the results show that they meet the requirement of 12bits 40MSPS pipeline ADC.