USB2.0 Host Controller ASIC Design

The USB has become a most popular bus standard in computer's peripheral interface.It has virtues of high speed,full speed,low speed,hot Plug and Play,using easily and etc.USB2.0 hardware system consists of USB host control chip and equipment interface control chip,i.e.peripheral device chip.It is very important to design the IP core of all USB function modules for the development of Soc field.In this paper,we introduce the design of AHB Interface USB2.0 Host Controller IP,which has great application foregrounds in embedded host,wireless USB and etc.Based on the analysis of USB1.x and USB2.0's principle,communication specification,types of transactions,power management etc,the hardware architecture of a USB2.0 AHB-interface host controller IP core is mainly presented.The IP core is divided into some modules,which have been coded by Verilog HDL and simulated by testvector.A system function verification testbench of the IP is presented in detailed, which is based on BFM.All kinds of testcase are generated to stimulate the IP core.As a result,the IP core meets USB specification in function and timing.Then based on TSMC0.18um standard cell library,we designed a corresponded hard core and explained some design details,such as synthesis & optimization,timing analysis,place and route steps,clock tree generated technique etc.The chip with a layout size of 40um~2 contains 50 thounsand logic gates.At the 120M clock,the circuit power consumption is 22mW.