ASIC Design Of Full Digital Three-Phase SPWM Signal Generation System

According to the requirement of power electronics, a three phase SPWM signal generation system is designed by using regular sampling. In previous, our team mainly finished system and module design by using Verilog HDL. At last, the IP soft core was generated and passed simulation and FPGA test. This thesis is mainly focused on ASIC design.By setting timing constraint and using Synopsys Design Compiler software, logic synthesis is performed and gate level netlist is streamed out, which is under the support of Chartered 0. 35um technology synthesis library. ROM is regarded as black box to synthesize. 10 PADs are inserted by using commands of tool and handy revising netlist.Place and rout is performed by using Synopsys Apollo software. Floorplan, macro cell placement, power floorplan, standard cell placement, clock tree synthesis, routing etc. flows are included in design. Metal density rule violations are solved by adding dummy metal. Antenna effect rule violations are solved by inserting diode. At last, layout pass DRC and LVS check, then, stream out GDSII and tape out in Chartered 0. 35um technology.SPWM IP soft core is performed front simulation. And netlist which is outputted from place and rout is performed post simulation. Post simulation waveform has 15.02ns delay time than system clock edge as add device andwire delay.The design is based on ASIC flow, and it is passed the test from algorithm to layout and chip. The chip has been taped out in Chartered 0. 35um technology, and the whole system reaches the following target: working frequency range is 10MHz to 50 MHz, dynamic power is 42. 32mW, area of chip is 1754. 6X1746. 2um2.