Research And Application Of The Function Verification In The IP Core Design

With the increasement of IC design complexity, difficulties of verification increased also. It's important for high efficient verification methods to improve IC design efficiency. On the other hand, the design methods of VLSIC turned to be a new mothod of SOC design based on IP reuse. IP design was made to be the new point of the IC industry. In order to improve the efficiency of whole IC design, the efficiency and correctness of IP design should be guaranteed, so the research of verification in the process of IP design became meaning. A kind of auto-compare testbench design was presented in this thesis, based on traditional function verification method, meanwhile it was applied to the design of a UART soft IP core. The correctness of IP core functions was verified by simulation.Firstly, IP design began with analyzing functions of UART. In this part, splitting function blocks, the connections among sub modules, and the detailed functions of each module were discussed. Secondly, the behavior module, the RTL module, and the verification module were built one function block after another by the way of design combining with verification. In the process of the block design, the waveform was output by the simulation environment to reflect the verification result. At last, all blocks were composed as a top module. Then the UART soft IP core and the auto-compare testbench were established.In this thesis, the system level description language SystemC was used as the language of the testbench design. The testbench design included building behavior module, verifying the functions of each module, sampling the data, and outputting the compared results. During the design, it was disclosed that the number of module codes described by SystemC was fewer than that by Verilog HDL. It showed that SystemC was important in improving code efficiency, and fastened the development of IP core.In some parts, the use of the soft design environment Modelsim was illustrated. From creating project document to waveform analysis, from simulating modules written in single language to that in multi-language, each step was absolutely necessary.Furthermore, a method that using the coverage analysis tool to improve the design efficiency of soft IP core was introduced in this thesis. At the same time, the analysis of the code structures proved that a fine code structure was important to the reuse and expansibility of the design. At the end, all contents were summarized, and some advices were given to proceeding deep researches of IP core design and verification.