Design And Verification Of DMA Controller For YHFT-matrix High Performance DSP Soft Core

YHFT-Matrix is a high-performance floating-point DSP(Digital Signal Processor) soft core developed by National University of defense technology with full independent intellectual property rights for wireless communications, video and image processing. To solve DSP data supply problem, we design a powerful move data components-Direct Memory Access Controller(DMAC)- for the DSP core. The main work and contribution include:1. Deeply analyze the DSP architecture and application requirements, complete the overall architecture design of the multichannel and multibus DMA controller, complete the parametric address design of the DMA controller.2. To meet the communication requirements of vector memory on the core and memories outside the core, we design two common channels which have different priority. They support matrix transpose operation to support matrix transpose operations directly. And they have the function of chaining and linking, that can satisfy the requirements of some complex data stream transmissions. 3. To meet the communication requirements of VM, ASRAM, DDR3 and from the antenna to send and receive data dedicated peripherals, we design a AXI dedicated channel, that can be connected to both AXI master and AXI slave, flexible to use. 4. To meet the requirements of Emulation/Test component access to DSP memory space, we design a ET dedicated channel. It supports multiple data read and write, with various addressing modes, that can facilitate ET function expansion in the future. 5. To ensure the function correctness of the design, we use two verification methods to fully verify the design, including simulation verification and assertion-based verification. Simulation verification has three levels: module level, component level and system level. The statistics of code coverage meets the requirement of the design. Interface protocol and bus arbitration are verified by assertion-based verification. The results show that the function of DMA controller is correct, which can meet the design requirements of the system. 6. We synthesize the design based on 45 nm technology library. The results show that, DMA controller working frequency can reach above 800 MHz, the total area of the design is 165411.5 um2, the total power consumption is 65.97 m W, that can achieve the expected goals of the design.