The Design And Power Consumption Optimization Of 12bit Analog-to-Digital Converter

As we all know,the system-on-chip design methodology has been shifted to mixed-signal type.It is necessary to integrated mixed-signal module and base-band processor in a signal chip especially in the field of wireless voice and digital communication.Chip of this type usually includes digital parts of digital and analog parts of analog base-band,power management,radio frequency(RF) and phase loop lock(PLL).Analog-to-digital converter(ADC) is one of the most important building blocks in portable devices where low power dissipation is an essential factor.With the development of Integrated Circuit technology,typical device size has reached deep sub-micrometer,and typical voltage has already lower than 1Ⅴ.The balance between power dissipation and circuit performance is a serious problem with the effect of noise and short channel effect.Pipeline ADC could achieve high speed and medium-to-high resolution,for it is serial in cascade stage and parallel as a whole.The special architecture paves the way for power optimization in system and in each module by various measures.The whole optimization including resolution distribution,capacitor scaling,and architecture selection of OTA and SHA and comparator is proposed to instruct the design of pipeline ADC.A 12-bit 200-MS/s pipeline converter is presented in 0.18μm CMOS from 1.8-V supply by the improved power optimization approach in which improved sample and hold amplifier and comparator are adopted to compensate the mismatch from capacitor and offset from capacitor.Test result indicates that it consumes 145mW at 50MS/s with 68.5dB SNDR,76.4dB SFDR under 40MHz input signal,while DNL and INL are within+0.6/-0.6 and+1/-0.6LSB respectively.