Analysis And Design Of CMOS Rail-to-Rail Operational Amplifier

Operational amplifier(op-amp) is the most widely used basic block in analog and mixed-signal-processing circuits. The over performance of many circuits and systems depends mainly on the quality of the op-amp used in their design. In the paper, a CMOS rail-to-rail op-amp has been analyzed and designed.Firstly, In order to realize the rail-to-rail input swing, an input stage has been proposed, which comprises two pairs of single n-channel differential pairs. The input stage does not need perfect matching between complementary differential pairs. To ensure constant transconductance over the entire input common-mode voltage range, the compensation circuit which is based on processing signal currents has also been designed. The technique is universal in that the constant transconductance can be obtained independent of I-V characteristic and is compatible with deep submicron CMOS devices. Using BSIM3v3 model of a standard CSMC 0.6μm DPDM CMOS process, the op-amp is simulated in detail by Cadence Spectre. The results show that the input /output swing of the op-amp circuit is rail-to-rail and the maximum deviation in transconductance is maintained within±5%, and the open loop gain can reach 122.6dB with unity gain bandwidth of 10.7MHz.Secondly, a CMOS bandgap reference circuit has been designed, which mainly provides reference voltage with low temperature coefficient to the op-amp. The principle of bandgap reference and inherent curvature in the first-order compensation has also been analyzed. A current-mode curvature-compensated bandgap reference has been designed and some important design considerations that might affect the accuracy of bandgap reference have also been discussed. Simulation results show that the temperature coefficient of output reference voltage is 7.69ppm/℃in wide temperature range, which meets the op-amp requirement.Finally, the elementary layout of the op-amp has also been designed, including the discussion on the MOS transistor mismatch model,the voltage and current match characteristic related to layout and the total layout design and check(such as DRC).