Based On Csmc0.6¦Ìm The Cmos Rail-to-rail Operational Amplifier Chip Design Research

Recently, the low-voltage design techniques in Analog IC Design have attracted more and more attention. As a common and important integrated cell circuit, the low-voltage design of the operational amplifier (Op-amp) has important reference and practical values. With the decrease of the voltage, however, the input and output dynamic range of the Op-amp will continuously reduce in the influence of the threshold voltage, which can seriously affect the normal operation of the post-stage circuit. In order to enhance the input and output dynamic range of the Op-amp, the design of the Rail-to-Rail Op-amp has become research hotspots.In this thesis, the Op-amp was designed and analyzed firstly. The constant transconductance of the Rail-to-Rail input stage, which is on the basis of the feed-forward compensation circuit, was performed for the input stage. The biasing circuit is with the wide-swing current-drain circuit. The output stage is with the feed-forward class AB output stage controlled by the floating current source. The compensating circuit is improved by the Miller compensation capacitor. Meanwhile, a voltage band-gap reference based on the current-mode curvature compensation was designed. The simulating results indicated that the temperature coefficient of the voltage band-gap reference is merely 7.69ppm/℃under the temperature range of-55 to 125℃.Thirdly, the DC characteristic, transient characteristic and the AC characteristics of the designed circuit were simulated and analyzed by using the standard CSMC 0.6μm CMOS technology process parameters. The simulation results revealed that the Op-amp meet the Rail-to-Rail input and output requirements. The Static power consumption is 1.079mW, the open-loop gain is 123.5dB, the unit-bandwidth product is 10.6MHz. and the phase margin is 54.8°.Finally, with the CSMC 0.6μm technology process, the cell unit of the circuit was designed on the basis of the basic theory of layout design and the specific requirements of the whole circuit. Meanwhile, according to full-chip ESD protection architecture, the ESD detection discharge circuit was designed based on the FOD. and the ESD protection device was also designed by using the SCR technology. Then the whole layout was verified by the design rule and the rationality was also checked.