Pipelined Adc Design And Research

Analog to Digital Converter(ADC) is the interface circuit of the analog signal converting to digital signal and used widely in the signal processing system. Because of its high speed,low power and high presion, pipelined ADC is paid for more attention.Based on research of the theory and structure of the 1.5bit/stage pipelined ADC, the model is studied and some blocks how to affect the result are analyzed. Also, a 10bit 60MHz pipelined ADC is designed and simulated and some block layouts are designed. Four parts of our discussions included in this paper are as follows:1,From the pipelined ADC theory, the theory of 1.5bit/stage and its technology of digital error logic are researched in details. The operational amplifier and the comparator in the pipelined ADC how to affect the result are discussed using the Simulink. Because of the structure and the performance of the designed ADC, the design techniques are used differently and some new techniques are introduced with the semiconductor technics and designing technology.2,Based on SMIC 0.18μm CMOS mixed-signal model, all the pivotal circuits in10bit 60MHz pipelined ADC are designed and simulated, mainly containing: (1) Bandgap; (2) Sample and Hold circuit; (3) Muti Digital to Analog Converter(MDAC); (4) Operational amplifier; (5) Comparator; (6) Boostrapped swtich. Sample and Hold circuit and operational amplifier are analyzed mainly. The noise of MDAC and resistor of switch are researched. Also, Sub-ADC,the non-overlapping circuit,delay array and digital error logic are designed. The output voltage of the bandgap vary 1.2mV from -40°to 125°in the TT corner and 5.3mV in the FF corner. Operational amplifier's bandwidth reach 400MHz and phase margin is 70°. The structure of A+BC in the digital error logic is new and simple and of small area compared with the one consisted of adder.3,The system simulation is done and the results show that at the ramp signal, the output of ADC do not lose code; at the sin signal 2MHz and the sample frequency of 60MHz, the output of ADC is reasonable and analyzed results prove the SFDR reaches 60dB. the static power comsumption is about 200mW. 4,Last, the layout of the some circuits are designed, containing bandgap,boostrapped switch,non-overlapping circuit and D-trigger. In the design of the layout, the device matching techniques and the antenna effect are introduced. Analog blocks and digital blocks are how to layout in the chip. The layout of all the chip should keep up with the direction of the signal.