Design And Verification Of DDR2 SDRAM Controller

The latest generation memory, DDR2 SDRAM, is cheap, speedy and with large capacity. However, it has some fatal defect by itself. The DDR2 SDRAM has a lot of parameters which must be carefully matched when operated. For solving this problem, there comes the DDR2C, DDR2 SDRAM Controller. DDR2C hides the complex operating timing and makes it possible for a chip to access the DDR2 SDRAM by a group of simple interface.This paper will study to implement a DDR2C with higher bandwidth and more easily operating. The content includes how to simply the DDR2 SDRAM operation and how to improve the bandwidth of DDR2 interface maximally. Therefore, the controller operates the four banks with round robin sequence, and intercrosses the active BANK command with the read/write command. At the same time, it runs in a fixed pipeline cycle with auto pre-charge command during the last three clock cycles. These two measures improve the bandwidth utilization greatly. The DDR2C designed in this paper can run at 200MHz stably in current medium performance FPGA chip. When connect to 16bit width of DDR2 SDRAM chip, this design can achieve the bandwidth of 3Gbit.