The Research And Implementation Of DDR2 SDRAM Controller

Memory, as an indispensable session in a computer, greatly affects the integrated performance of a computer. As the frequency of memory is increasing, the technique demands for the controller have been gradually increased. The operation on DDR2 SDRAM, which related to a number of time parameters and state transformations, is quite complicated. Therefore, the issue, that how to read and write effectively, stably and quickly from the DDR2 SDRAM, becomes a hot and meaningful research direction.This thesis aims to research and develop a DDR2 SDRAM controller, which could be transplantable and able to be read and write correctly. Through studying DDR2 SDRAM controller systemically, this thesis proposed a top-down designing method, using Verilog Language to describe, and Modelsim was used to verify the function. Afterword, the Quartus II software was used to verify the designed controller on Altera StratixII EP2S180F1020 platform, which is a multi-cores verification platform that designed by our laboratory.During design process, the controller was designed as a combination of three different functional major modules, containing a controller module, a data path module and an I/O module. Correspondingly, the major modules were fractionized into sub modules according to diverse specific function. Inclusively, the controller module contains an initialization module and a read/write path module; the data path module contains a read path module and a write path module and the I/O module contains a write interface and a read interface module. Thereby, the architecture of the controller was explicated after multiple functional division and modularization, which was also conductive to the implementation and debugging. When it refers to some key techniques, such as the asynchronous FIFO solves the match problem between the internal and external clock in the architecture of data path module, and also plays a role as data buffer and data integration. The design of I/O module interface uses a single-fold clock to transmit data through rising and falling edges, in contrast to the traditional utilization of multiplier clock. The explanation of the methods of accomplishment of each module was given in the process of the design. The readers may find it is easy to understand through the expounding of architecture diagram and pseudo-code.After completing the design of controller, Verilog Language was used to verify the function. During the function verification process, a DDR2 SDRAM model provided by Micron Company was used for the function verification. The simulation result indicates that a series of functions, such as reading, writing and auto refreshing, were achieved correctly. The post-simulation also presented an excellent performance on timing verification with 200MHz clock frequency on Quartus II.