Design And Verification Of DDR2 SDRAM Controller Based On LCoS Timing Color Display

The Liquid Crystal on Silicon(LCoS)chip is a microdisplay chip developed on the basis of silicon-based liquid crystal technology.It is commonly used in electronic products such as wearable devices,and has advantages such as low power consumption and high display resolution.The most commonly used display mode of LCoS chip is RGB space color display.Any pixel in RGB color space can represent a color.The disadvantage of the RGB space color is that the color of the pixel is likely to change.The LCoS time-series color display utilizes the temporal sensation of the human eye,synthesizes high-speed sequential three-primary light into colored light,giving a person a feeling of stable color image.This paper designs a Double Data Rate II(DDR2)memory controller that can embed LCoS display chip based on LCoS timing color display.It contains a write data host and 6 read data host with Advanced Microcontroller Bus Architecture(AMBA)bus structure to provide relevant read and write instructions,addresses and data for the slave.The controller configures DDR2 enabled self-refresh and auto-refresh modes,and offers five low-power modes.In low-power mode,the controller does not provide high-speed differential clocks to DDR2 memory.The design is based on the DDR2 protocol specification,and the system spec and sub-module specs are written.The design adopts a modular design method.The DDR2 controller mainly includes the physical layer and the protocol layer.Each layer is subdivided into functional submodules.The operating mode switching module in the protocol layer automatically enables the low power mode according to the system status.The protocol layer also contains a command queue for queuing instructions sent by each read/write host based on priority and then sent to DDR2 memory.The physical layer contains a digital phase-locked loop,which will provide a more accurate data synchronization signal to DDR2 memory,while its data segmentation module will provide differential clock and data signals.Based on the detailed understanding of the internal structure and basic working principle of DDR2 memory and the study of the DDR2 SDRAM JEDEC protocol JESD79-2F,each functional module program of the DDR2 controller of this subject is designed using the Verilog hardware description language.Synopsys' VCS tool was used to simulate and verify the function of each controller module code,then write script files.using DC logic synthesis tool to translate,optimize and map the controller code in cell library,and completeing the testing of the chip after taping out.