The Design And Verification Of A High Performance DDR2 SDRAM Controller

In order to meet the demand of high capacity storage,most system design needs external memory.However,the bottleneck of system performance is also the external memory.With the increasing demand of the computer system to a higher speed and density,"memory wall" becomes a serious problem.Memory is difficult to satisfy the processor high speed,high bandwidth and large capacity for data access and memory,so it has great limit for computer system.DDR2 SDRAM has higher bus speed,lower voltage and double data prefetching than DDR1,therefore,DDR2 SDRAM memory is the main external memory in the PC memory.The paper analyses the characteristics and applicability of various memory controller access scheduling methods on the basis of DDR2 SDRAM protocol,finally proposing a four dynamic access queue scheduling method based on the memory controller access dynamic scheduler[4]according to the DDR2 own access method and management strategy.The four cache queue make the controller be able to check request sequences in advance,by optimizing the management strategy to improve the page,and the optimized controller can cross access bank.The controller dynamically schedules DDR2 SDRAM access and allows active command and precharge command out of order according to pending requests,current request and request recorder to solve controller waste cycles,thereby reducing the DDR2 SDRAM precharge time and greatly improving the utilization rate of the bus.The article uses Verilog description language to describe memory controller optimization design and carry on comprehensive function verfication to ensure the correctness and completeness of memory controller,validation results show that the optimized scheduler when core frequency is 200 MHZ and burst length is 4 of DDR2 SDRAM is reduced at least 2 clock cycles than Open Page strategy in different rows of the continuous access to the same bank,reduced most 6 clock cycles,and is at least reduced 7.5 clock cycle than Close Page in the same row of continuous access to the same bank,the optimized controller can realize cross access bank,access delay is reduced at least 6 clock cycles than un-optimized schedule in continuous access to different bank.