The Research And Implementation On DDR2 Memory Controller With High Bandwidth And Low Latency

The access speed of memory has become an important factor affecting the performance of processor, and the performance of the main memory depends on the memory controller. The main goal of our work focuses on DDR2 SDRAM controllers which can match the need of X-2 processor's bandwidth and latency. Full use of the mechanism of DDR2 SDRAM in the system is very important to exert and improve the utility of X-2 processor, whose data transfers on both positive and negative edges of clock. This thesis proposes a new controller which can tranfer data with higher bandwidth and lower latency to DDR2 SDRAM.This thesis studies the architecture of memory system in X-2 processors, and analyzes the development of memory controller in the current international market and the technical specification of DDR2 SDRAM controller in details. Now the implementation of the new DDR2 SDRAM controller is finished. In this memory controller, when it receives initial instructions from CPU, it will configure operating parameters for DDR2 SDRAM and issues sequence of initial instructions to memory. Then, the controller can receive read or write instructions from processor. According to the state of the accessed bank, it generates SDRAM instructions. Finally, the controller will send a instuction to DDR2 SDRAM and a later instruction for a certain while satisfied time interval. If the present instruction is read or write, the controller needs to transfer data and control data strobe signal simultaneously.The design of DDR2 memory controller in X-2 processor includes functional organization, logic design and verification. This thesis discusses the design of the controller deeply. Based on the current implementation we designed the controller which is consisted of the transfer layer and the physical layer, fitting the access pattern of streaming processor. The transfer layer is responsible for converting the instructions of CPU to a series of SDRAM instructions. The physical layer sends the instructions to DDR2 SDRAM and controls their timing.The DDR2 memory controller in X-2 processor is implemented in Verilog and performance test of module and system on the ModelSim SE 5.7d and nc_verilog tools which ensures the correctness of design. At last, this thesis proposes some schemes aiming at amend the drawbacks of architecture of the controller.After producing X-2 processor, preliminary testing shows that the design of DDR2 SDRAM controller is correct and its performance suits the assumption.