The Design Of DDR2-SDRAM Controller Based On RF Auto-Test Platform

An effective RF auto-test platform need a high speed data acquisition system. As the sampling rate growing higher, The system employ high-capacity memories such as Dynamic RAMs (DRAMs) to cope with increasing data sizes of modern designs. Due to the feature of the RF auto-test platform, its memory sub-system must have large capacity, high bandwidth and hard real-time performance. Therefore, it has an important significance to design a DDR2-SDRAM controller with low latency.The operating feature of the RF auto-test platform determines its DDR2-SDRAM controller must have multi access port, and each port has the same low latency requirement. As a reason that the data transfer of the platform is continuous data stream, we partition the physical address space following the internal structure of the DRAM device, making accesses temporally predictable and temporally isolated. And then the TDMA arbitration, static command sequence and new refresh mechanism are used that can significantly reduces worst-case access latency. After finishing hardware design, this thesis does a simulation to the new DDR2-SDRAM controller. Simulation result shows that when using the 400MHz DDR2-SDRAM DIMM, it has a bandwidth of 1.9GBps, which is 60% of the data bus bandwidth. And the worst-case access latency is under 200ns.This thesis solve the high-latency problem in normal memory controller. It can be used not only in the RF auto-test platform, but also the other real-time systems.