Design And Implementation Of DDR2 SDRAM Controller

Liquid Crystal on Silicon(LCOS)is a display technology which combines the advantage of Liquid Crystal Display(LCD)and semiconductor technologies.It is a new promising flat panel display technology to be applied in portable mobile electronic devices and 3D technology,due to high resolution,small size and low power consumption.A DDR2SDRAM controller is embedded in the LCOS display chip to solve the response time requirements of the color sequence LCOS display.This subject comes from the internship company.According to the demand of the LCOS SoC projects in the internship company,the DDR2SDRAM controller is designed in this thesis,based on the basic operation and sequence requirements of the DDR2 SDRAM defined by the standard specification.The designed controller could be compatible with the model number MT47H64M16HR-25E,a data bit width of 16 bit and 1 GB capacity.Besides,the back-end physical implementation based on the SMIC 55 nm process is carried out according to the project tasks.The designed DDR2 SDRAM controller consists of user interface module,initialization module,control module,read-write data module and I/O interface module in this thesis.The control module is the core of the entire controller circuit and is mainly divided into state transition module,refresh module and counter modules.The user interface conversion module uses the asynchronous FIFO composed of dual-port RAM as the data cache unit,which solves the problem of frequency mismatch between the user and the controller.Besides,the use of two different frequency clocks completes the design of the data conversion circuit and solves the problems of single edge data and double-edge data conversion.In addition,the use of the structure of the delay chain achieves the center alignment of the data signal and data strobe signal,which ensures the correct sampling of data.After the functional specification and other modules'definations of the project,the RTL code is designed and verified by simulation.After that,the SMIC 55 nm process and over-constrained technology are used to complete the logic synthesis,which obtains the netlist file.At the same time,the reports of timing,area,and power consumption are given.According to the global planning of the LCOS chip,the Cadence company's Encounter tool was used to complete the physical implementation of the controller.Because in the deep sub-micron process,crosstalk between lines can not be ignored,and the clock signal is the interconnect with largest load and highest turn-over frequency in the entire design,the crosstalk has the greatest impact on the clock signal.According to the analysis of the integrity of the clock signal,the clock interconnect is designed to reduce the crosstalk on the clock signal line by using 2 times the line width and 2 times the pitch.After the physical design was completed,static timing analysis,formal verification,and physical verification of the DDR2 SDRAM controller were completed using the PT,Formality,and Calibre tools.Besides,the post-emulation was performed on critical timing paths.By the SMIC 55 nm technics,the power consumption of the DDR2 SDRAM controller designed in this thesis is5.26 mW.The area is 5.08×104?m~2,and the clock frequency of the main clock is 333 MHz.